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This project proposes to reintroduce timing predictability as a first-class property of embedded processor architectures. To fully exploit such timing predictability, however, would require a significant redesign of much of computing technology, including operating systems, programming languages, compilers, and networks. Obviously, a three-year NSF project cannot address the full breadth of the problem. We propose, therefore, to tackle the problem from the hardware design perspective. Our approach will be to develop precision timed (PRET) machines as soft cores on FPGAs, and to show that using such machines software components can be integrated with what would traditionally have been purely hardware designs. We expect that this will first greatly improve the expressiveness and usability of FPGA-based design flows, and second will provide a starting point for a decades-long revolution that will once again make timing predictability an essential feature of processors.