Profs. Carloni and Shepard awarded NSF grant to study communication networks for multi-core systems-on-chip
05/22/2006
Prof. Luca Carloni (CS) and Prof. Kenneth Shepard (EE) have been awarded a three-year NSF grant to study the design of low-power scalable communication networks for multi-core systems-on-chip.
During the past decade, interconnects have replaced transistors as the dominant determiner of integrated circuit performance by imposing primary limits on latency, energy dissipation, signal integrity and design productivity for giga-scale systems integration. Scalable networks made of carefully-engineered links are expected to replace traditional on-chip communication schemes by providing higher bandwidth with lower power dissipation. Further, on-chip networks offer the opportunity to mitigate the complexity of system-on-chip design by facilitating the assembling of multiple processing cores through the emergence of standards for communication protocols and network access points. This project will investigate the design of low-power scalable on-chip networks for multi-core systems-on-chip by combining a new low-latency, low-energy, current-mode signalling techniques with the design of latency-insensitive protocols extended to support fault-tolerant mechanisms.
The project is funded by the NSF Foundations of Computing Processes and Artifacts (CPA) Cluster. In 2005 the NSF CPA cluster received 532 proposals and funded approximately 10% of them.
The NSF CPA cluster supports research and education projects to advance formalisms and methodologies pertaining to the artifacts and processes for building computing and communication systems. Areas of interest include: topics in software engineering such as software design methodologies, tools for software testing, analysis, synthesis, and verification; semantics, design, and implementation of programming languages; software systems and tools for reliable and high performance computing; computer architectures including memory and I/O subsystems, micro-architectural techniques, and application-specific architectures; system-on-a-chip; performance metrics and evaluation tools; VLSI electronic design and pertinent analysis, synthesis and simulation algorithms; architecture and design for mixed media or future media (e.g., MEMs and nanotechnology); computer graphics and visualization techniques.